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论文:2023,Vol:41,Issue(5):1024-1032 |
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引用本文： |
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吴乐宁, 王淼, 陈福. Chisel构建处理器模型的功能验证方法研究[J]. 西北工业大学学报 |
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WU Lening, WANG Miao, CHEN Fu. Research on functional verification method processor model built by Chisel[J]. Journal of Northwestern Polytechnical University |
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| Chisel构建处理器模型的功能验证方法研究 |
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| 吴乐宁1, 王淼2, 陈福1 |
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1. 航空工业西安航空计算技术研究所, 陕西 西安 710076;
2. 西北工业大学 计算机学院, 陕西 西安 710072 |
| 摘要: |
| 随着航空硬件设计复杂度的提高,芯片验证技术已经成为了芯片设计的难点。为了有效缩短设计流程的总体工作时间,有必要在占据设计大量时间的验证中,研究出快速寻找设计错误的方法。被测设计是兼容ARM V4指令集架构(instruction set architecture,ISA)的处理器模型ARMChisel,该处理器模型采用新型的硬件语言Chisel构建,是一个具有高复杂性的硬件设计。基于这一嵌入式处理器模型:①设计了支持ARM V4 ISA架构全部指令的随机指令生成器,提高了生成测试激励的速度;②根据新型构建语言Chisel的特点,针对被测处理器模型设计了Chisel层面初级验证、覆盖率快速验证、直接测试验证和复杂应用程序验证策略,确保达到预期的覆盖率;③在Chisel环境和Verilog环境中搭建了基于嵌入式处理器模型的测试平台,测试平台收集覆盖率同时能快速准确地发现错误并定位错误,提高了验证速度。采用FPGA(field programmable gute array)方法加速大型应用程序的验证,缩短了验证周期。 |
| 关键词:
Chisel
处理器模型验证
ARM架构
指令生成器
测试激励
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| Research on functional verification method processor model built by Chisel |
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| WU Lening1, WANG Miao2, CHEN Fu1 |
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1. AVIC Xi'an Aeronautics Computing Technique Research Institute, Xi'an 710076, China;
2. School of Computer Science, Northwestern Polytechnical University, Xi'an 710072, China |
| Abstract: |
| With the increasing complexity of hardware design, verification has become the difficulty of chip design. In order to effectively shorten the overall working time of the design process, it is necessary to work out a method to quickly find design errors in the verification that takes up a lot of time in the design. The design under test is an ARM Chisel compatible with the ARM V4 instruction set architecture (ISA) processor model. The processor model is built with a new hardware language Chisel and is a highly complex hardware design. Based on this embedded processor model, ①a random instruction generator supporting all instructions of the ARM V4 ISA architecture is designed to increase the speed of generating test stimuli; ②based on the characteristics of the new construction language Chisel, designed for the processor model under test four verification stages: primary verification at the Chisel level, rapid verification of coverage, direct test verification and verification of complex applications, to ensure that the expected coverage is achieved; ③built in the Chisel environment and Verilog environment based on the embedded processor model Test platform. The test platform can quickly and accurately find errors and locate errors while collecting coverage, which improves the verification speed. Finally, the FPGA acceleration method is used to accelerate the verification of large-scale application programs and shorten the verification cycle. |
| Key words:
Chisel
processor model validation
ARM architecture
instruction generator
test stimulus
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| 收稿日期: 2022-12-01
修回日期:
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| DOI: 10.1051/jnwpu/20234151024 |
| 通讯作者: 陈福(1984—),航空工业西安航空计算技术研究所高级工程师,主要从事机载嵌入式软件研究。e-mail:cfu12435@163.com
Email：cfu12435@163.com |
| 作者简介: 吴乐宁(1994—),航空工业西安航空计算技术研究所助理工程师,主要从事机载嵌入式软件研究。
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| 相关功能 |
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| 作者相关文章 |
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| 吴乐宁 在本刊中的所有文章 |
| 王淼 在本刊中的所有文章 |
| 陈福 在本刊中的所有文章 |
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