论文:2022,Vol:40,Issue(2):369-376
引用本文:
范毓洋, 邓智, 李子航. 机载电子跨时钟域同步电路验证及可靠性分析[J]. 西北工业大学学报
FAN Yuyang, DENG Zhi, LI Zihang. Verification and reliability analysis of synchronizers in clock domain crossing[J]. Northwestern polytechnical university

机载电子跨时钟域同步电路验证及可靠性分析
范毓洋1,2, 邓智1, 李子航1,2
1. 中国民航大学 民航航空器适航审定技术重点实验室, 天津 300300;
2. 中国民航大学 适航学院, 天津 300300
摘要:
在航空器的机载设备中存在大量的多时钟域电路,数据在进行跨时钟域传输时可能会产生亚稳态,导致数据传输错误,电路可靠性降低。但亚稳态导致的故障具有偶发性、不易重现,且现有的跨时钟域专用验证软件使用成本高昂,不支持三模冗余场景下的跨时钟域电路验证。针对此问题,提出了一种基于传统工具的寄存器传输级(RTL)验证、板级加速测试和计算评估相结合的方法。该方法能够在设计早期使用通用仿真工具发现三模应用场景或正常场景下的跨时钟域传输问题,并评估潜在跨时钟域传输风险,降低了高安全等级机载复杂电子验证经济成本和时间成本,提高电路可靠性。
关键词:    机载电子    跨时钟域    寄存器传输级验证    可靠性   
Verification and reliability analysis of synchronizers in clock domain crossing
FAN Yuyang1,2, DENG Zhi1, LI Zihang1,2
1. Civil Aircraft Airworthiness and Repair Key Laboratory of Tianjin, Civil Aviation University of China, Tianjin 300300, China;
2. Airworthiness College, Civil Aviation University of China, Tianjin 300300, China
Abstract:
There are a large number of multi-clock domain circuits in the airborne equipment of aircraft. When data is transmitted across the clock domain, meta-stability may occur, resulting in data transmission errors and reduced circuit reliability. However, due to the occasional and non-reproducible faults caused by metastability, and the high cost of existing cross-clock domain specific verification software, cross-clock domain circuit verification in three-mode redundancy scenarios is not supported. To solve this problem, a method that combines register transfer level (RTL) validation, board-level accelerated testing and computational evaluation based on traditional tools is presented. This method can detect the cross-clock domain transmission problems in three-mode application scenarios or normal scenarios and assess potential cross-clock domain transmission risks using generic simulation tools at an early stage of design. It reduces the cost of economy and time for high safety level airborne complex electronic verification, and improves the reliability of the circuit.
Key words:    airborne electronics equipment    clock domain crossing(CDC)    register transfer level (RTL) verification    Reliability   
收稿日期: 2021-07-09     修回日期:
DOI: 10.1051/jnwpu/20224020369
基金项目: 航空科学基金(20182667009)资助
通讯作者:     Email:
作者简介: 范毓洋(1988-),中国民航大学助理研究员,主要从事机载电子适航设计验证与软错误防护研究。e-mail:fanyuyang1988@126.com
相关功能
PDF(1906KB) Free
打印本文
把本文推荐给朋友
作者相关文章
范毓洋  在本刊中的所有文章
邓智  在本刊中的所有文章
李子航  在本刊中的所有文章

参考文献:
[1] WU J, MA Y, ZHANG J, et al. Research on metastability based on FPGA[C]//Proceedings of 2009 9th International Conference on Electronic Measurement & Instruments, 2009
[2] STEININGER S, SCHWENDINGER M. A systematic approach to clock failure detection[C]//Proceedings of 2019 Austrochip Workshop on Microelectronics, 2019
[3] GINOSAR R. Metastability and synchronizers:a tutorial[J]. IEEE Design & Test of Computers, 2011, 28(5):23-35
[4] OMAR R, JASON H A. High-level synthesis of FPGA circuits with multiple clock domains[C]//Proceedings of 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
[5] DATTA G, CONG H L, KUNDU S, et al. qCDC:metastability-resilient synchronization FIFO for SFQ logic[C]//Proceedings of 2019 IEEE International Superconductive Electronics Conference, 2019
[6] FAA. Simple and complex electronic hardware approval guidance[S]. Order8110.105A
[7] RTCA. Designed assurance guidance for airborne electronic hardwar[S]. DO-254-2000
[8] DORIS Chen, DESHANAND Singh, JEFFREY Chromczak, et al. A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs[C]//Proceedings of Symposium on Field Programmable Gate Arrays, Monterey, 2010
[9] 肖安洪, 曾辉, 秦友用, 等. 基于FPGA的"龙鳞"通信模块跨时钟域验证实践[J]. 上海交通大学学报, 2019, 53(增刊1):84-87,103 XIAO Anhong, ZENG Hui, QIN Youyong, et al. Cross-clock domain verification practice of naspic communication module based on FPGA[J]. Journal of Shanghai Jiao Tong University, 2019,53(suppl 1):84-87,103 (in Chinese)
[10] 张启晨. 静态形式验证在跨时钟域和复位验证中的应用[J]. 中国集成电路, 2019, 28(4):38-43 ZHANG Qichen. Application of static formal method in CDC and reset verification[J]. China Integrated Circuit, 2019, 28(4):38-43 (in Chinese)
[11] 罗莉, 何鸿君, 徐炜遐, 等. 面向SOC芯片的跨时钟域设计和验证[J]. 计算机科学, 2011, 38(9):279-281 LUO Li, HE Hongjun, XU Weixia, et al. Design and verification of clock domain crossing for SOC[J]. Computer Science, 2011, 38(9):279-281 (in Chinese)
[12] 梁骏, 唐露, 张明. 基于随机延时注入的跨时钟域信号验证方法[J]. 微电子学与计算机, 2014, 31(2):1-4 LIANG Jun, TANG Lu, ZHANG Ming. A random delay injection based clock domain crossing verification method[J]. Micro-electronics & Computer, 2014, 31(2):1-4 (in Chinese)
[13] LI Y B, NELSON B, WIRTHLIN M. Synchronization techniques for crossing multiple clock domains in FPGA-Based TMR circuits[J]. IEEE Trans on Nuclear Science, 2010, 57(6):3506-3514
[14] RTCA. Software tool qualification considerations[S]. DO-330-2011
[15] JENNIFER S. Understanding metastability in FPGAs[EB/OL]. (2018-12-20)[2021-3-25]. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01082-quartus-ii-metastability.pdf?wapkw=Understanding%20Metastability%20in%20FPGAs.
[16] BEER S, GINOSAR R, PRIEL M, et al. The devolution of synchronizers[C]//2010 IEEE Symposium on Asynchronous Circuits and Systems, 2010
[17] CUMMINGS C E. Simulation and synthesis techniques for asynchronous FIFO design[EB/OL].(2002-06-16)[2021-02-18]. http://www.sunburst-design.com/papers/