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论文:2019,Vol:37,Issue(3):515-522 |
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引用本文： |
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谢天娇, 李波, 杨懋, 闫中江. 存储紧缩性高速QC-LDPC译码器的FPGA实现[J]. 西北工业大学学报 |
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XIE Tianjiao, LI Bo, YANG Mao, YAN Zhongjiang. Memory Compact High-Speed QC-LDPC Decoder Based on FPGA[J]. Northwestern polytechnical university |
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| 存储紧缩性高速QC-LDPC译码器的FPGA实现 |
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| 谢天娇1,2, 李波1, 杨懋1, 闫中江1 |
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1. 西北工业大学 电子信息学院, 陕西 西安 710072;
2. 中国空间技术研究院西安分院, 陕西 西安 710010 |
| 摘要: |
| 提出了一种高速部分并行准循环低密度奇偶校验码（quasi-cyclic low density parity check codes，QC-LDPC）译码器架构和该架构下的2种紧缩性存储策略，采用将多个相邻行的硬判决码字和外信息压缩到一个存储单元、硬判决待输出码字信息紧缩性存储及相对应的高速译码器架构，不仅减少了用于硬判决码字的存储块的数量，而且可以便于一个时钟周期内对多个数据同时进行访问并处理，从而提高了译码器的数据处理吞吐量。通过采用Xilinx XC4VLX160 FPGA 实现CCSDS标准中的LDPC译码器验证了文中提出的这种紧缩性存储策略及其高速译码器架构可以有效地利用FPGA资源来实现高速译码器，实现结果显示该译码器在布局布线后时钟频率可以工作在250 MHz，译码器采用14次迭代，对应2 Gb/s的译码吞吐量。 |
| 关键词:
QC-LDPC码
LDPC译码器
BRAM存储器
FPGA
CCSDS
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| Memory Compact High-Speed QC-LDPC Decoder Based on FPGA |
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| XIE Tianjiao1,2, LI Bo1, YANG Mao1, YAN Zhongjiang1 |
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1. School of Electronics and Information, Northwestern Polytechnical University, Xi'an 710072, China;
2. China Academy of Space Technology, Xi'an 710010, China |
| Abstract: |
| In this paper, two compact memory strategies for partially parallel QC-LDPC decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle so as to increase the throughput of decoder. We demonstrate significant high speed and area efficient benefits of using the proposed techniques with an FPGA implementation of a CCSDS LDPC decoder on Xilinx XC5VLX330 device. The result shows that our new decoder can operate at a maximum frequency of 250 MHz after place and route, and achieve a throughput up to 2 Gb/s at 14 iterations. |
| Key words:
quasi-cyclic low density parity check codes (QC-LDPC)
LDPC decoder
BRAM memory
FPGA
CCSDS
hard decisions
throughput
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| 收稿日期: 2018-05-20
修回日期:
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| DOI: 10.1051/jnwpu/20193730515 |
| 基金项目: 国家自然科学基金（61771390，61501373，61771392，61271279）、国家科技重大专项（2016ZX03001018-004）与中央高校基本科研业务费（3102017ZY018）资助 |
| 通讯作者:
Email： |
| 作者简介: 谢天娇(1983-),女,西北工业大学博士研究生,中国空间技术研究院西安分院高级工程师,主要从事卫星组网跨层设计和信道编译码算法及硬件实现技术研究。
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| 相关功能 |
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| 作者相关文章 |
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| 谢天娇 在本刊中的所有文章 |
| 李波 在本刊中的所有文章 |
| 杨懋 在本刊中的所有文章 |
| 闫中江 在本刊中的所有文章 |
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参考文献: |
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[14] CCSDS. Low Density Parity Check Codes for Use in Near-Earth and Deep Space Applications[S]. CCSDS 131.1-O-2, 2007 |
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1．谢天娇, 李波, 杨懋, 闫中江.高速码率兼容DVB-S2的LDPC译码器的FPGA实现[J]. 西北工业大学学报, 2019,37(2): 299-307 |
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