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论文:2021,Vol:39,Issue(3):510-520 |
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引用本文： |
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王时雨, 张盛兵, 黄小平, 常立博. 星载SAR成像与智能处理的单片多处理架构[J]. 西北工业大学学报 |
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WANG Shiyu, ZHANG Shengbing, HUANG Xiaoping, CHANG Libo. Single-chip multi-processing architecture for spaceborne SAR imaging and intelligent processing[J]. Northwestern polytechnical university |
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| 星载SAR成像与智能处理的单片多处理架构 |
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| 王时雨, 张盛兵, 黄小平, 常立博 |
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| 西北工业大学 计算机学院, 陕西 西安 710072 |
| 摘要: |
| 星载SAR图像智能处理系统需对成像和多种不同任务应用进行在轨实时处理，设计高效专用单芯片多处理器能够有效支持实时性和低功耗的要求，片上数据组织和访存结构是设计重点。分析了SAR成像CSA（chirp scaling）和神经网络VGG-11 2种典型模型，抽象出遥感图像智能处理过程的协同计算模型。设计了一种带状Tile化数据处理方案及专用多处理架构，提出了一种Tile划分及多Tile同步拼接策略，设计了处理单元之间数据缓存结构，极大降低片外访存带宽，支持多任务模型的并行流水执行。芯片采用28 nm工艺，整体功耗仅为1.83 W，吞吐率和能效分别达到9.89 TOPS和5.4 TOPS/W。该架构可提高在轨遥感智能处理平台的实时性，降低系统设计复杂度，根据算法模型的不同，可灵活适应差异化扩展。 |
| 关键词:
单片多处理器
领域专用
智能遥感
带状数据划分
数据填充
灵活扩展
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| Single-chip multi-processing architecture for spaceborne SAR imaging and intelligent processing |
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| WANG Shiyu, ZHANG Shengbing, HUANG Xiaoping, CHANG Libo |
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| School of Computer Science and Engineering, Northwestern Polytechnical University, Xi'an 710072, China |
| Abstract: |
| The satellite-borne SAR image intelligent processing system needs to process on-orbit real-time imaging and various tasks of applications, for which reason designing a dedicated high-efficient single-chip multi-processor is of prioritized necessity that can simultaneously satisfy requirements of real-time and low power consumption. Aiming at on-chip data organization and memory access structure, two typical models of SAR(synthetic aperture radar) imaging CSA (chirp scaling) and neural network VGG-11 are analyzed, and then a collaborative computing model for the intelligent processing on remote sensing is extracted. A strip Tile data processing scheme and a dedicated multi-processing architecture is not only proposed, but a data organization and a caching strategy of Tile space synchronization splicing is also presented. In addition, the designed data caching structure among the processing units greatly reduces off-chip access memory bandwidth while supporting parallel pipeline execution of multi-task model. The chip adopts 28 nm CMOS technology featuring with merely 1.83 W of the overall power consumption, whose throughput and energy efficiency reaches 9.89TOPS and 5.4 TOPS/W, respectively. The present architecture can improve real-time performance of the on-orbit remote sensing intelligent processing platform while reducing the complexity of system designing, which is highly adaptive to differentiated expansions according to different models of algorithm. |
| Key words:
chip multi-processors
domain-specific
intelligent remote sensing
strip tiling
data filling
flexible extensibility
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| 收稿日期: 2020-09-28
修回日期:
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| DOI: 10.1051/jnwpu/20213930510 |
| 通讯作者:
Email： |
| 作者简介: 王时雨(1984-),西北工业大学博士研究生,主要从事高性能微处理器架构、VLSI/SOC设计与测试研究。
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