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论文:2019,Vol:37,Issue(2):299-307 |
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引用本文： |
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谢天娇, 李波, 杨懋, 闫中江. 高速码率兼容DVB-S2的LDPC译码器的FPGA实现[J]. 西北工业大学学报 |
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XIE TianJiao, LI Bo, YANG Mao, YAN Zhongjiang. LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA[J]. Northwestern polytechnical university |
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| 高速码率兼容DVB-S2的LDPC译码器的FPGA实现 |
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| 谢天娇1,2, 李波1, 杨懋1, 闫中江1 |
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1. 西北工业大学 电子信息学院, 陕西 西安 710072;
2. 中国空间技术研究院 西安分院, 陕西 西安 710100 |
| 摘要: |
| 提出了一种基于现场可编码门阵列（field programmable gate Array，FPGA）的高速码率兼容第二代数字电视广播（digital video broadcast：second generation，DVB-S2）标准的低密度奇偶校验码（low density parity check codes，LDPC）译码器架构，通过对DVB-S2的LDPC码校验矩阵进行初等变换得到新的矩阵，由准循环（quasi-cyclic，QC）子矩阵和行变换下三角双对角子矩阵（transformation of staircase lower triangular，TST）组成。提出的译码器架构QC部分利用现阶段研究最多的准循环QC-LDPC译码器技术，而对于TST部分，只需兼容QC矩阵部分，提出的架构可以按照QC的架构而动态地改变TST的并行路数，而且分开存储TST与QC的更新消息，保证了码率兼容。基于Xilinx XC7VX485T FPGA的验证结果表明，5种码率兼容的DVB-S2 LDPC译码器，可到达时钟频率250 MHz，最大迭代次数20次，对应的译码器最大吞吐量为2.5 Gbit/s。 |
| 关键词:
高速LDPC译码器
码率兼容
DVB-S2标准
FPGA
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| LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA |
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| XIE TianJiao1,2, LI Bo1, YANG Mao1, YAN Zhongjiang1 |
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1. School of Electronics and Information, Northwestern Polytechnical University, Xi'an 710072, China;
2. China Academy of Space Technology(Xi'an), Xi'an 710100, China |
| Abstract: |
| A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works. |
| Key words:
high speed LDPC decoder
rate-compatible
DVB-S2 standard
FPGA
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| 收稿日期: 2018-04-12
修回日期:
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| DOI: 10.1051/jnwpu/20193720299 |
| 基金项目: 国家自然科学基金（61501373，61771390，61771392，61271279）、国家科技重大专项（2016ZX03001018-004）与中央高校基本科研业务费项目（3102017ZY018）资助 |
| 通讯作者:
Email： |
| 作者简介: 谢天娇(1983-),女,西北工业大学博士研究生,中国空间技术研究院西安分院高级工程师,主要从事卫星组网跨层设计和卫星信道编译码算法及硬件实现技术研究。
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| 相关功能 |
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| 作者相关文章 |
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| 谢天娇 在本刊中的所有文章 |
| 李波 在本刊中的所有文章 |
| 杨懋 在本刊中的所有文章 |
| 闫中江 在本刊中的所有文章 |
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参考文献: |
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