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论文:2015,Vol:33,Issue(6):1049-1054 |
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引用本文： |
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陈庆宇, 吴龙胜. 一种细粒度流水化控制的FPU集成方法[J]. 西北工业大学学报 |
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Chen Qingyu, Wu Longsheng. A Method of FPU Integration Based on Fine-Grained Pipeline Control[J]. Northwestern polytechnical university |
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| 一种细粒度流水化控制的FPU集成方法 |
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| 陈庆宇, 吴龙胜 |
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| 西安微电子技术研究所, 陕西 西安 710065 |
| 摘要: |
| 解决了在RISC处理器中嵌入高精度FPU的问题,提出一种细粒度的基于集中控制和分段数据处理的扩展双精度FPU集成方法,该方法通过细分浮点指令的执行状态,然后以执行状态为基本粒度生成与之对应的FPU控制信息,最后根据控制信息分段处理目标操作数,并通过流水化的形式实现数据的回写。基于一款SPARC V8型微处理器对上述方案进行了设计实现、仿真验证及分析。结果表明,该FPU集成方法与公开文献的方案相比,浮点指令关键路径缩短61%,硬件消耗减小16.9%,浮点计算效率提高1.7倍,可用于将扩展双精度FPU集成到RISC处理器中,并使两者高效协同运算。 |
| 关键词:
FPU
协同运算
细粒度
集中控制
流水回写
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| A Method of FPU Integration Based on Fine-Grained Pipeline Control |
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| Chen Qingyu, Wu Longsheng |
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| Xi'an Microelectronics Technology Institute, Xi'an 710054, China |
| Abstract: |
| Double-precision floating-point can hardly satisfy the accuracy requirement of contemporary scientific computing. It deserves further study about how to get the higher precision FPU embedded into the RISC processor and about how to make an effective collaborative computing between them. A fine-grained integration method of extended double-precision FPU is proposed in this paper; it is based on centralized control and segmented data processing. The method finely differentiates the execution status of floating instructions and generates the FPU control information corresponding to execution status of floating-point instructions in fine-grain. Then, destination operands are segmentedly processed and written back register is implemented and the implementation is explained with a flowchart. An SPARC V8 processor based on the proposed mechanism has been implemented, verified and analyzed. The results and their analysis show preliminarily that the critical path of floating instructions decreases 61%, hardware consumption declines 16.9% and the floating-point calculation efficiency increase 1.7 times. |
| Key words:
algorithms
calculations
computer architecture
computer hardware
controllers
cost reduction
data processing
digital arithmetic
efficiency
exchange coupling
flowcharting
microprocessor chips
real time control
scalability
schematic diagrams
state estimation
time delay
centralized control
collaboration computing
fine-grain
FPU
pipeline write-back
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| 收稿日期: 2015-04-24
修回日期:
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| DOI: |
| 通讯作者:
Email： |
| 作者简介: 陈庆宇(1988—),西安微电子技术研究所博士研究生,主要从事高性能飞行控制SoC设计及系统级可靠性研究。
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参考文献: |
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[1] Bailey D H. High-Precision Floating-Point Arithmetic in Scientific Computation[J]. Computing in Science & Engineering, 2005, 7(3): 54-61
[2] 王重阳. 单、双、扩展精度自适应浮点乘、除和开方运算单元的实现[D]. 北京:华北电力大学, 2011 Wang Chongyang. Realization of Adaptive Floating-Point Multiplication, Division and Square Root Unit for Single, Double and Extended Precision[D]. Beijing: North China Electric Power University, 2011 (in Chinese)
[3] Aeroflex. UT699 LEON 3FT/SPARC V8 Microprocessor Functional Manual[M]. Aeroflex Inc, 2012
[4] Kane G, Heinrich J. MIPS RISC Architectures[M]. Prentice-Hall, Inc, 1992
[5] Boersma M, Kroner M, Layer C, et al. The POWER7 Binary Floating-Point Unit[C]//2011 20th IEEE Symposium on Computer Arithmetic (ARITH), 2011:87 - 91
[6] Ramakrishnan A, Conrad J M. Analysis of Floating Point Operations in Microcontrollers[C]//Southeastcon, 2011 Proceedings of IEEE, 2011: 97-100
[7] Joven J, Strict P, Castells-Rufas D, et al. HW-SW Implementation of a Decoupled FPU for ARM-Based Cortex-M1 SoCs in FPGAs[C]//2011 6th IEEE International Symposium on Industrial Embedded Systems (SIES), 2011: 1-8
[8] Schwarz E M, Schmookler M, Trong S D. FPU Implementations with Denormalized Numbers[J]. IEEE Trans on Computers, 2005, 54(7): 825-836
[9] Trong S D, Schmookler M S, Schwarz E M, et al. P6 Binary Floating-Point Unit[C]//IEEE Symposium on Computer Arithmetic, 2007: 77-86
[10] 赵勇, 张盛兵, 王党辉. 微处理器浮点IP核集成设计[J]. 微电子学与计算机, 2006, 23(7):129-133 Zhao Yong, Zhang Shengbing, Wang Danghui. The Integration of Floating Point IP in Microprocessor Design[J]. Microelectronics & Computer, 2006, 23(7): 129-133 (in Chinese)
[11] Gajjar N, Devahsrayee N M, Dasgupta K S. Scalable LEON 3 Based SoC for Multiple Floating Point Operations[C]//2011 Nirma University International Conference on Engineering (NUiCONE), 2011:1-3
[12] 杜学亮, 金西. 向量浮点协处理器VFP-A的设计和验证[J]. 微电子学, 2009, 39(5):597-601 Du Xueliang, Jin Xi. Design and Verification of Vector Floating Point Coprocessor VFP-A[J]. Microelectronics, 2009, 39(5):597-601 (in Chinese)
[13] Gaisler J. The LEON-2 Processor User's Manual[M]. Sweden, Gaisler Research Inc, 2003
[14] Hennessy J L, Patterson D A. Computer Architecture: A Quantitative Approach[M]. Holland, Elsevier, 2012
[15] Internationa S. The SPARC Architecture Manual Version 8[M]. SPARC International Inc, 1998
[16] Gaisler J, Catovic E, Isomaki M, et al. GRLIB IP Core User's Manual[M]. Gaisler Research, 2007 |
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